1. Field of the Invention
The present invention relates to a 3D chip stack with fuse-type through silicon via (TSV) structures and, more particularly, to a 3D chip stack with programmable fuse-type TSV structures used to carry electrical signals vertically through semiconductor die.
2. Background and Related Art
In the packaging of electronic devices, such as, semiconductor chips and wafers, or semiconductor chip carriers, vertical interconnection to the next packaging level, whether it be to a chip carrier or stacked chip, may be achieved by through silicon vias (TSVs). Various techniques are known to create TSVs. Stacking chips is a multi-story chip structure, sometimes referred to as a 3D chip stack, allows for reduced signal transmission distance from die to die and enables a large increase in the number of links that may be established between dies.
Such small-sized packages, as provided by 3D chip stacks using TSV structures, are in high demand for a variety applications, such as, cell pone, digital cameras, PDAs, GPSs, laptop computers, and the like. The continuation growth of these applications requires on-going efforts to boost performance, broaden functionalities, reduce cost and increase packaging densities.
One of the difficulties with such structures is that when the 3D stack is assembled, the interconnects between chips are formed by prefabricated TSVs. As a result, it is not possible to alter the status of these TSVs, once assembled. However, for purposes of repairing, programming, altering status and rerouting, it is desirable to have the capability to open an originally shorted TSV line.